This paper proposes two power-efficient digital classifier designs for a neural network-based sleep apnea (SA) detection system. The digital classifiers designed in this work are rectified linear unit (ReLU) and signum (sign), which are used in the hidden layer and the output layers, respectively of our proposed binarized neural network model (BNN). The BNN model yielded around 88% accuracy using the selected classifiers with balanced evaluation metrics. Studies of measurement results such as accuracy, power consumption, and comparison with other widely used classifiers such as hyperbolic tangent (tanh) and sigmoid were conducted on digital hardware using a general-purpose field-programmable gate array (FPGA) called Nexys Artix-7. By proposing our binarizing technique called Shift-Accumulate-based Binarized Neural Network (SABiNN) on the neural network model and using the stacked multiplexer design method with look-up-tables for both ReLU and sign classifiers, the power consumption rates of the selected classifiers were significantly reduced without compromising performance. The 4-hidden layer 2-(8-126-4)-1 BNN model consumed a maximum of 5 W of power with a thermal margin of 11.4 °C including a low resource utilization report. The proposed classifier designs demonstrate promising results in accurately modeling neural network models that enable SA detection, offering the potential for cost-effective and scalable healthcare solutions.

Design of a Power-Efficient Digital Classifier for Neural Network-Based Sleep Apnea Detection System

Pullano S. A.;
2024-01-01

Abstract

This paper proposes two power-efficient digital classifier designs for a neural network-based sleep apnea (SA) detection system. The digital classifiers designed in this work are rectified linear unit (ReLU) and signum (sign), which are used in the hidden layer and the output layers, respectively of our proposed binarized neural network model (BNN). The BNN model yielded around 88% accuracy using the selected classifiers with balanced evaluation metrics. Studies of measurement results such as accuracy, power consumption, and comparison with other widely used classifiers such as hyperbolic tangent (tanh) and sigmoid were conducted on digital hardware using a general-purpose field-programmable gate array (FPGA) called Nexys Artix-7. By proposing our binarizing technique called Shift-Accumulate-based Binarized Neural Network (SABiNN) on the neural network model and using the stacked multiplexer design method with look-up-tables for both ReLU and sign classifiers, the power consumption rates of the selected classifiers were significantly reduced without compromising performance. The 4-hidden layer 2-(8-126-4)-1 BNN model consumed a maximum of 5 W of power with a thermal margin of 11.4 °C including a low resource utilization report. The proposed classifier designs demonstrate promising results in accurately modeling neural network models that enable SA detection, offering the potential for cost-effective and scalable healthcare solutions.
2024
binarized neural network
digital classifier
FPGA
Sleep apnea
software-hardware co-simulation
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.12317/97962
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